This invention relates to a semiconductor integrated circuit device having a function for monitoring an internal signal which is not output to the outside of the device during the normal operation, and also relates to a method for monitoring the internal signal.
In semiconductor integrated circuit devices, the internal signal of a circuit formed on a silicon chip is generally monitored to estimate the characteristics of the circuit or perform failure analysis. There are some internal signal monitoring methods--a method for bringing a pico-probe into circuit wiring to thereby observe a signal waveform using an oscilloscope; a method for incorporating, in advance, a monitoring pad in a circuit node to be observed to thereby observe a signal waveform which appears in the monitoring pad; etc. In these methods, however, the internal signal cannot be monitored unless the silicon chip is exposed, i.e. if it is packaged.
While the refining of semiconductor devices is being advanced, the securing of their reliability is being considered more and more important, and therefore various reliability tests are being performed. To analyze a failure, if any, by the reliability tests, it is necessary to reproduce the failure. Since in the aforementioned methods, however, it is necessary to break the package so as to expose the silicon chip, which means that the atmosphere of the circuit formed on the chip changes and hence the failure may not be faithfully reproduced. To avoid this, a method is employed in which a test mode for monitoring the internal signal (an internal signal monitoring function) is beforehand provided in a semiconductor integrated circuit device as one of the operation modes, and the test mode is used to output an internal signal from its external terminal in order to enable observation of the internal signal with the package sealed. This test mode is used by a mender when they perform failure analysis, and not usually by a user.
FIG. 1 is a block diagram illustrating the structure of a semiconductor integrated circuit device, specifically a semiconductor memory, with a monitor function for monitoring its internal signal.
As is shown in FIG. 1, a pad 10 receives, from the outside, a predetermined reference signal that has a half level of the power voltage. Input buffer circuits 30 refer to the reference signal applied to the pad 10 to thereby determine the logic level of input signals ADR[0]-ADR[n] applied from the outside to pads 20 and then to convert them into signals of a level appropriate for the device dealing with them. A memory circuit 40 is a circuit which functions during the normal operation. This circuit receives an address from the outside via the input buffer circuit group 30, thereby performing a predetermined operation and outputting storage data (an output signal). A test mode controlling circuit 50 is used to generate a test mode in the device. This circuit determines the operation mode on the basis of a signal input from the outside via the input buffer circuit group 30, thereby outputting a test signal indicative of a test mode. A selecting circuit 70 selects an internal signal appearing at a predetermined internal node 40N of the memory circuit 40 when the test signal from the test mode controlling circuit 50 has been activated, and selects the regular output signal of the memory circuit 40 when the test signal has been deactivated.
In the conventional device, an input signal from the outside is input to the memory circuit 40 via the input buffer circuit group 30 during the normal operation, and the memory circuit 40 performs a predetermined operation. At this time, the test signal from the test mode controlling circuit 50 is in the deactivated state, and the selecting circuit 70 selects the regular output signal of the memory circuit 40. Accordingly, the regular output signal is output to the outside via the pad 80.
To monitor the internal signal of the memory circuit 40, input signals ADR[0]-ADR[n] are set from the outside so as to satisfy predetermined conditions (such as a predetermined combination of logical values of input signals, a predetermined inputting order of the input signals, etc.). As a result, the test mode is made as an entry into the test mode controlling circuit 50, and the test signal from the circuit 50 is activated. When the test signal has been activated, the selecting circuit 70 selects the internal signal, which means that the internal signal is monitored.
Usually, the semiconductor device is mounted on, for example, a printed circuit board (PCB) together with other devices, and a bus, for example, is commonly used between the devices. There is a case where an operation noise from another device is input via the bus, with the result that the test mode is erroneously generated. Once the test mode is generated, it is kept activated and the semiconductor device malfunctions unless a process sequence for terminating the test mode is performed. Further, when the test mode has been erroneously generated, the internal signal is output to the outside of the semiconductor device, instead of the regular output signal. Any other device which has received the output internal signal malfunctions. Specifically, where the external terminal that outputs the internal signal functions as an input terminal during the normal operation, the input level of any other semiconductor device which uses the common bus connected to the input terminal deviates from its appropriate level. Further, where the external terminal that outputs the internal signal functions as an output terminal during the normal operation, the input level of any other semiconductor device which receives a signal from the output terminal deviates from its appropriate level.